This application claims benefit of Japanese Patent Application No. 2000-027539 filed on Feb. 4, 2000, the contents of which are incorporated by the reference.
The present invention relates to flip-flop circuits and, more particularly, to flip-flop circuits which can be constructed as high density and low power consumption semiconductor integrated circuits (ICs).
The flip-flop circuit (hereinafter abbreviated as FF circuit for the brevity sake) is one of the basic constituent elements of digital circuits, and various types of FF circuits have been proposed and used for various purposes.
Electronic devices and electronic application devices are in a trend of operation speed increase and performance improvement. Conventional high speed logic circuits usually use bipolar transistor logic circuits such as ECLs (Emitter-Coupled Logics). However, recent size and weight reduction of electronic devices and spread of battery-driven portable electronic devices, have led to increasing demand for logic circuits using MOS (Metal Oxide Semiconductor) transistors (hereinafter abbreviated as MOSTs) capable of integration density increase and power consumption reduction.
Prior art examples of such flip-flop meeting the above demand are disclosed in Japanese Patent Laid-Open No. 56--86527, Japanese Patent Laid-Open No. 1-248820 and Japanese Patent Laid-Open No. 4-16016. Furthermore, a DSL (Differential Split Level) circuit as shown in FIGS. 5A and 5B has been proposed.
FIG. 5A is a circuit showing a latch circuit L3 in an FF circuit. This latch circuit comprises an input circuit having three n-type MOS transistors (nMOSTs) 41 to 43, a CVSL (Cascade Voltage Switch Logic) circuit having a pair of nMOSTs 46 and 47 and a pair of p-type MOST transistors (pMOSTs) 48 and 49, the two transistor pairs being connected such that their inputs and outputs are in a crossing relation to one another, and nMOSTs 44 and 45 connected between the outputs of the input and CVSL circuits. The gate voltage on the nMOSTs 46 and 47 are set to Vdd/2+Vtn. Voltages on the drains of the nMOSTs 42 and 43, i.e., nodes D3P and D3N, can be raised only up to Vdd/2 even when they are at xe2x80x9cHxe2x80x9d (high) level. This potential is inputted to the gates of the pMOSTS 48 and 49, so that the pMOST 48 and 49 are not perfectly turned off. Thus, the outputs of these pMOSTs undergo fast changes, and operate substantially simultaneously. The other nMOSTs are effectively turned on because their gates are close to the ground level. The output of the latch circuit is thus determined by the difference between the currents in the two pMOSTs 48 and 49.
FIG. 5B is a block diagram showing an FF circuit, which is constructed by using two latch circuits L3 as shown in FIG. 5A. As shown, in this circuit the two latch circuits L3 are connected in cascade, and clock signals CP and CN are inputted to clock terminals of the first and second stage (i.e., master and slave) latch circuits L3, respectively. Input data signals DP and DN are fed to the master latch circuit, and output data QP and QN are obtained from the slave latch circuit.
However, in the above prior art circuit the potentials at the nodes D3P and D3N are determined by the nMOSTs when they are at xe2x80x9cLxe2x80x9d (low) level and by the pMOSTs when they are at xe2x80x9cHxe2x80x9d (high) level. This poses a problem that the operation speed is adversely affected by fluctuations of the nMOSTs and pMOSTs. In addition, the pMOSTs are slow in operation speed compared to the nMOSTs. Therefore, as for the potential changes at the nodes D3P and D3N the rising is delayed after the falling, thus posing a problem in the high speed operation. Furthermore, the amplitudes of the output signals QP and QN are substantially (GNDxe2x88x92Vdd), which is disadvantageously too large for the high speed operation.
An object of the present invantion is therefore to provide a flip-flop (FF) circuit of a high density semiconductor integrated circuit (IC) with fast operation and low power consumption.
According to an aspect of the present invention, there is provided a flip-flop circuit comprising a pair of latch circuits each including a push-pull circuit input stage and a hold circuit output stage, the pair latch circuits being cascade connected as a master latch and a slave latch so as to be operable under control of a clock signal from a clock line.
The input stage of each latch circuit has two pairs of nMOS transistors or nMOSTs with push-pull data inputted thereto and connected in series/parallel connection, the series/parallel connection being connected via an nMOST with a clock signal inputted thereto between positive supply voltage side and ground. The input stage of each latch circuit has two pairs of nMOSTs, these pairs each receiving push-pull data inputted thereto, the nMOSTs in each of the pairs being connected in series between the positive supply voltage side and the ground, and a pair of clock controlled series nMOSTs each connected between the juncture of the nMOSTs in each pair and the output stage.
According to another aspect of the present invention, there is provided a flip-flop circuit comprising a latch circuit each having the above input stage, the latch circuit being cascade connected in an arbitrarily combination. The hold circuit in the latch circuit includes a CVSL circuit having two pairs of nMOSTs and a pair of pMOSTs and an nMOST connected between the CVSL circuit and ground, which is controlled by a clock signal.
The flip-flop circuit further comprises an input circuit having two pairs of nMOSTs and connected to the data input side of the master latch circuit, an output circuit having two pairs of nMOSTs and connected to the data output side of the slave latch circuit, and an input circuit having two pairs of nMOSTs and connected to the clock line of the two latch circuits.
The flip-flop circuit further comprises a buffer circuit inserted in the clock line to equalize the delay times in the master latch circuit and the clock line.
In the flip-flop, a plurality of cascade connections each of the master and slave latch circuits are connected in parallel and controlled by a common clock line.
Other objects and features will be clarified from the following description with reference to attached drawings.